ECE + Business Honors @ UT Austin

Krithik Sama

ECE student interested in FPGA acceleration, RTL design/verification, AI hardware, and hardware-aware ML, with hands-on experience in quantization, model-to-RTL workflows, FPGA validation, and performance optimization across FPGAs and Arm CPUs.

Austin, TX

Featured work

Projects

The NBA FPGA Accelerator web interface, showing game-prediction controls — serial port, season/team filters, and a "Predict on FPGA" button that runs inference on the physical board.

Summer 2026 – Present

NBA Game Prediction on FPGA

A win-probability and point-spread predictor trained on 30K NBA games, quantized and compiled to RTL, and verified bit-exact on a Basys 3 board.

67%
Accuracy: 13 µs
Latency @ 100 MHz: 90.5%
LUT utilization: +0.171 ns
WNS

fpga
ml-hardware
rtl
verification

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fpga

Summer 2026 – Present

dwn2rtl — Checkpoint-to-Verilog Compiler for Weightless Neural Networks

A pip-installable compiler that maps a trained weightless neural network straight to Verilog, one 6-input neuron to one FPGA LUT6, verified bit-exact against a golden model in simulation and on-board.

1:1 → LUT6
Neuron mapping: 166K bit-exact
On-board vectors: Q3.12
Fixed-point format

fpga
ml-hardware
eda
research

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Scatter plot of accuracy versus LUT area for the sweep, with a highlighted Pareto frontier line tracing the best accuracy achievable at each area budget, annotated with the specific configuration at each frontier point.

Summer 2026 – Present

dwn-fpga-study — FPGA Design-Space Exploration for Weightless Neural Networks

A 77-build automated sweep across width, encoder resolution, fan-in, depth, and clock target — built on the dwn2rtl compiler — to find the actual accuracy/area frontier instead of guessing at it.

77
Builds swept: −40% (−0.24 pts acc.)
LUT savings: 58.6 → 100.9 MHz
Fmax

fpga
ml-hardware
eda
research

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Diagram of the SS2D cross-scan on the Mamba-3 recurrence, showing the four traversal orders (row-forward, row-reverse, column-down, column-up) and each direction's impulse response and combined reach across a 48x48 token grid.

Summer 2026

ARM-Scan — Optimized Mamba Selective-Scan Kernel

An Arm-optimized selective-scan kernel for Mamba, fusing the forward and reverse recurrences and tuned for NEON SIMD and multicore execution on Graviton4.

~1.7×
Scan fusion speedup: 18.9×
SISO speedup: 38.7×
Multicore scaling

systems
ml-hardware
software

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Force-directed placement of the ibm01 benchmark converging over 150 steps, shown alongside a cost-convergence chart tracking proxy cost per step down to its best value.

Spring 2026 – Summer 2026

Macro Placement Optimization Challenge

Bayesian optimization and adaptive local search on top of DREAMPlace, cutting proxy placement cost 16% versus RePlace with a 1000× faster per-move evaluator.

16% vs RePlace
Proxy-cost reduction: 1000×
Eval speedup: +3.2%
LNS improvement

eda
research
software

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A themed diagram of the Basys 3 board running the fish market announcer, labeling the bouncing 7-segment display, mode-advance button, pause button, and reset button.

Summer 2026

Tsukiji Fish Market Announcer

An auctioneer display for a Tsukiji-style fish market, built entirely in Verilog on a Basys 3 — scrolling variable-length messages across a 4-digit alphanumeric display.